1. Field of the Invention
The present invention relates generally to semiconductor memories and in particular to a flash memory system having improved characteristics.
2. Background Art
Semiconductor memories have been developed which are non-volatile and can be electrically programmed and erased. Electrically Programmable Read Only Memories (EPROM) exist which provide non-volatile operation and which have a small cell area so that data may be stored at a relatively high density. However, EPROMs are erased in bulk by exposing the entire cell array to U.V. light. Thus, these devices must be entirely reprogrammed every time an erasure occurs.
By way of further example, Electrically Erasable Programmable Read Only Memories (EEPROM) exist which are non-volatile and which can be electrically erased on a byte-by-byte basis. However, EEPROM devices have various shortcomings, including the lack of ability to store date at higher densities. This is due largely to the fact that each memory cell must have an associated select transistor. Thus, EEPROM devices are typically not capable of storing data at high densities.
Flash memory cells have also been developed which are non-volatile and which are capable of storing data at a relatively high density. However, most flash memory arrays are bulk erased although certain arrays permit erasure of less than the entire array. In addition, many flash memory arrays have reduced endurance, i.e., the ability to withstand repeated program-erase cycles, as compared to other types of semiconductor memory cells. Further, most large flash memory arrays have severe speed limitations during read operations due to the parasitic capacitance of the long bit lines used in the arrays.
The foregoing advantages and limitations of flash memory cells can best be illustrated by reference to the drawings. FIG. 1A shows a simplified typical conventional flash memory cell, generally designated by the numeral 10. Cell 10 is formed in an N type substrate 12. A P type well 14 is formed in substrate 12 followed by the formation of an N+ type region 16 in the well which functions as the source and another N+ type region which functions as the drain. The region 14a in the well 14 intermediate the source 16 and drain 18 regions functions as the cell channel region.
A polysilicon floating gate 20 is disposed over the channel region 14a and is insulated from the channel region by a thin gate oxide 22. This thin oxide, which is typically about 100 .ANG., is a key distinguishing feature of a flash memory cell. A polysilicon control gate 24 is disposed over the floating gate 20 and is insulated from the floating gate by an interpoly dielectric layer 26.
FIG. 1A also illustrates typical voltages which can be applied to cell 10 in order to program the cell. A relatively large positive voltage Vpp, +12 volts for example, is applied to the control gate 24. An intermediate voltage, +6 volts for example, is applied to the drain region 18 and the source region 16 is grounded. The P well 18 is biased to ground level by way of a P+ contact 28.
The large positive voltage applied to the control gate 24 causes hot electrons to be injected from the source region 16 towards the drain region 18. Some electrons pass through the gate oxide 22 in that portion of the channel region 42a near the drain region 18 and into the floating gate 20. As will be explained later, the presence of the negative charge on the floating gate alters the threshold voltage of the cell thereby indicating that the cell has been programmed. Cell 10 will remain programmed until it is erased as depicted in FIG. 1B.
Referring to FIG. 1B, this figure shows typical voltages for erasing cell 10. The source region 16 and the drain region 18 are left open (floating) and an intermediate positive voltage, +3 volts for example, is applied to the P-well 14. A relatively large negative voltage Vee, typically -15 volts, is applied to the control gate 24. These voltages cause electrons to be transferred from the floating gate 20 and through the thin gate oxide 22 and into the positive P-well along the channel 42a. The predominate mechanism for erasing in the manner previously described is commonly referred to as cold electron injection or Fowler-Nordheim tunneling. Other types of conventional erasing sequences result in tunneling concentrated in the vicinity of the drain region 18.
It is known that the endurance of the flash memory cell can be improved by erasing and programming the cells at different locations. The exemplary configuration of FIG. 1A results in programming near the drain region 18. The exemplary configuration of FIG. 1B results in erasure over the entire channel 14a so that erasure and programming do not completely occur at the same location. However, as just noted, other exemplary erase configurations would result in the majority of the erase and programming mechanism taking place near the drain region, thereby resulting in reduced cell durability.
FIG. 1C depicts the manner in which cell 10 is read. The drain region 18 is connected to an intermediate level positive voltage, such as +3 volts, by way of a load impedance represented by resistors 30A and 30B. The resistors divide down the +3 volts to approximately +1.5 volts at the drain region 18. An intermediate positive voltage, such as +3 volts, is applied to the control electrode 24 and the source region 16 is grounded.
In the event the cell 10 has not been previously programmed, the cell will have an erased threshold voltage VtErase which is relatively low. The voltage applied to the cell will be sufficient to invert the channel 14a, that is, to render the cell 10 conductive. A current will be drawn through load 30A/30B and will produce a voltage at the inverting input of a sense amplifier 32, also connected to the drain region 18, which is less than the +1.5 volts present when the cell is non-conductive at of a reference voltage VRef. The output of the sense amplifier will change state thereby indicating that the cell had not been programmed but, rather, was in the erased state.
In the event cell 10 had been previously programmed, the negative charge present on the floating gate 20 due to the presence of electrons will increase the threshold voltage of the cell. The increased threshold voltage, referred to as VtWrite, will prevent the cell 10 from becoming conductive when the voltages of FIG. 1C are applied. Thus, the voltage applied to the inverting input of amplifier 32 will remain high at +1.5 volts. Reference voltage Vref is selected to be less than +1.5 volts so the amplifier output will remain unchanged indicating that the cell had been programmed.
FIG. 2 shows a conventional flash memory array of a memory system with control circuitry deleted. The array, which has a capacity of 1 Megabit, is comprised of N channel cells 10 as depicted in FIGS. 1A-1C. The floating gate cells 10 are arranged in 1024 rows and 1024 columns to form a 1 megabit array. In the exemplary array, all of the cells 10 have their source regions connected to a circuit common. All of the cells 10 located in a particular column have their drain regions connected to a common bit line BL1-BL1024. The bit lines may be implemented by way of a metal bit line or by way of a buried doped semiconductor line. All of the cells 10 located in a particular row have their control gates connected to a common word line WL1-WL1024. The word lines are typically implemented by way of a doped polysilicon lines.
The manner in which the cells 10 are erased, programmed and read is well known in the art and is similar to that described in connection with FIGS. 1A-1C. Since all of the sources of the cells 10 are connected together, all cells 10 of the array must be erased together in this arrangement. As previously noted, there are flash cell arrays which do permit blocks of cells to be erases but it does not appear that any flash cell arrays permit individual cells to be erased if desired.
When the individual cells 10 of the FIG. 2 array are read, a positive voltage is applied to the selected bit line BLN (the bit line connected to the target cell), with the deselected bit lines being grounded. During consecutive read cycles, it is invariably necessary to rapidly swing the voltage of the bit lines BLN between ground and the positive voltage used in read operations.
Since memory program and memory erase operations require at least an order of magnitude more time than do memory read operations, flash memory devices are primarily intended to function as read mostly devices. That is, once the device has been programmed, it is anticipated that almost all of the subsequent operations will be read operations. Thus, the speed of memory read operations essentially determines the overall speed of the memory for all practical purposes.
One of the primary limitations on reading speed is the inherent capacitance associated with the memory bit lines BLN. Some of this capacitance is attributable to the capacitive coupling between the associated bit line and the surrounding structure, with the remainder of the capacitance being attributable to the capacitance of the drain region of all of the cells 10 connected to the bit line BLN. This capacitance is particularly large in the exemplary FIG. 2 array in that the bit line extends the full length of the array and is connected to each of the 1024 cells located in the associated array column.
The delays associated with the capacitance are exacerbated when the bit lines have a significant resistance. The resultant large RC time constant significantly impedes the speed of memory read operations, particularly when the bit line BLN is implemented in the form of a doped semiconductor line, either diffused or ion implanted, rather than a metal line.
One approach to overcoming such speed limitation is to use memory cells that produce large currents when read. These large currents decrease the time necessary to charge and discharge the bit lines. However, large cell currents inherently require large geometry cells. Large geometry cells obviously result in a decrease in the number of cells which can be implemented in an integrated memory device and further result in the undesirable parasitic capacitance previously discussed.
It is also known that the effects of bit line capacitance can be reduced by segmenting the bit line. By way of example, FIG. 3 shows part of a prior art memory cell array utilizing a segmenting technique. Only part of a single array column is depicted, namely, a column associated with a bit line BL1. The array includes a Segment 1 comprising rows 1-32 of cells 10 and a Segment 2 comprising rows 33-64 of the cells. Other segments can be added as required and the size of the segments can be increased to include 64, 128, etc. rows in each segment. Further, the number of columns present in each segment can be increased.
Each segment is connected to the associated bit line BL1 by a segment select transistor, with Segment 1 being connected by way of transistor 12 and Segment 2 connected by way of transistor 14. Depending upon the read address, only one of the segments is selected at one time by way of appropriate segment select transistors SS1, SS2, etc. Thus, the total capacitance associated with the bit lines is substantially reduced. By way of example, if Segment 1 is selected, select transistor 12 is made active with the remaining select transistors being maintained off. Thus, only the capacitance associated with the drains of cells 1-32 plus the additional capacitance of transistors SS1, SS2, SS3-SSN must be charged and discharged during the read operation. Bit line BL1 still extends the full length of the array, but the capacitance attributable to the bit line alone is significantly smaller than that associated with the drain regions of the cells 10 of the non-selected segments.
There has also been a tendency in the prior art to reduce the area required of a memory array by alternating metal bit lines and diffused semiconductor bit lines. Since metal bit lines require much more area to implement than do semiconductor bit lines, the use of alternating metal and semiconductor lines reduces the area of each cell significantly. Such arrays, which are used in EPROMs, are sometimes referred to as alternate metal virtual ground or AMG arrays.
FIG. 4 shows an exemplary prior art AMG array of memory cells 10. The array includes multiple segments including a Segment 1 comprising rows 1-64 and columns of cells. An actual array would include many more columns. The next segment is Segment 2 and includes rows 65-128, with only one row being depicted. Typically, there would be additional segments in the AMG array.
The cells 10 in a row are arranged in pairs, with each pair sharing a common source region. By way of example, adjacent cells 10A and 10B located in the row associated with word line WL2 include a common N type source region. Cell pair 10E and 10F located in the row associated with word line WL3 also share a common N type source region diffusion which is connected by a buried N type semiconductor bit line BLB to the common source region diffusion of cells 10A and 10B. Similarly, cells 10B and 10C in adjacent cell pairs have a common N type drain region diffusion which is connected by a buried N type semiconductor bit line BL2 to the common drain region of cells 10F and 10G.
Alternate bit lines, including line BL1, BL2 and BL3 are each connected in parallel with an overlying metal track (not shown). The metal tracks are connected to the buried bit lines by way of contacts 16 located at the top and bottom of each segment.
Each segment of the conventional AMG array has an associated set of segment select transistors SSN which are controlled by complementary segment select signals SN and SN. The segment select signals are controlled by address decoding circuitry so that only one of the array segments will be enabled during a read or write operation. When Segment 1 is enabled, a selected one of signals S1 and S1 is active and the other segments select signals SN and SN are inactive. Similar segment select transistors are located on the opposite side of each segment and are connected in parallel with the transistors located at the top of the array and are driven by the same select signal SN and SN. This parallel arrangement of segment select transistors at opposite sides of the bit lines tends to reduce the effect of bit line resistance by one-half.
Operation of the AMG array can best be described by way of example. Assume that cell 10B is to be read. Control circuitry (not depicted) will cause a positive voltage to be applied to bit line BL2 by way of a load circuitry (also not depicted). This voltage will thus be applied directly to the drain region of cell 10B. The control circuitry will also ground bit line BL1. The remaining bit lines BLN are also maintained at the same positive voltage as bit line BL2. Segment select signal S1 will be active (high) and S1, by definition will be inactive. Thus, segment select transistor SS1 will be rendered conductive and transistor SS1 will remain off. Conductive transistor SS1 will connect the source region of cell 10B to grounded bit line BL1. In addition, the control circuitry will connect a positive voltage to word line WL2.
Assuming that cell 10B is in an erased state, the above conditions will render cell 10B conductive. Current will flow from bit line BL2, through the cell, into bit line BLB, through transistor SS1 to the grounded bit line BL1. Sense circuitry will detected the resultant change in voltage at the load connected to bit line BL2 thereby sensing the state of cell 10B.
The deselected word lines of the array are all grounded so that the cells of the deselected rows will remain non-conductive irrespective of programmed state. With respect to cell 10A in the selected row, this cell will remain non-conductive since both the drain and source of the cell are at ground potential. This is also true of the cells in the selected row to the left of selected cell 10A. Cell 10C will remain non-conductive since conductive transistor SS2 will cause both the source and drain to be at the same positive voltage. With respect to cell 10D, as previously noted, the deselected bit line BLN, with the exception of line BL1, are at the same positive potential as bit line BL2 so that both the drain and source of the cell are at the same potential as are the other cells in the row to the right of cell 10D. Thus, these deselected cells will remain non-conductive.
Programming of selected cell 10B is accomplished by bringing bit line BL2 to a positive voltage and grounding the remaining bit lines BLN through a high impedance load. A large positive voltage is applied to the selected word line WL2 and the deselected word lines are grounded. Again, select signal S1 is made active and S1 inactive so that line BLB connected to the source of cell 10B is at ground potential and the drain connected to bit line BL2 is at a positive potential. This combination of voltages will cause cell 10B to be programmed. The cells in the deselected rows will not be programmed since the deselected word lines are all grounded. With respect to cell 10A in the selected row, the source and drain will be at the same low potential so that programming will not take place. Cell 10C will not be programmed because the drains and sources of the cells will be at the same high potential due to transistor SS2 being conductive. Cell 10D will have its source at a high potential and its drain presented with a high impedance to ground so that it will also not become programmed.
It can be seen that when successive memory cell reads take place, it is likely that one or more of the bit lines BLN will have to switch between high and low level states. Although the bit lines have a relatively low resistance by virtue of the overlying metal bit track connected in parallel, the bit lines extend over the full length of the array, interconnecting each of the array segments, including the relatively high capacitance of each cell of the array connected to the bit lines. Since, as previously noted, the time required to carry out read operations is the limiting factor in the overall speed performance of this type of read mostly memory, it can be seen that the AMG array speed is reduced.
The AMG array is capable of achieving a high cell density but suffers from a speed disadvantage due to the bit line capacitance previously described. A memory array which provides both the density of AMG arrays, but minimizes the speed shortcomings of such arrays would be highly desirable.
The present invention is directed to a flash memory system which addresses the above-noted shortcomings of conventional flash memory systems by providing the capability of erasing only two bits, a single byte or the entire array in one sequence. Further, the endurance of the cells 10 is enhanced by virtue of the fact that programming and erasing take place on substantially different locations on the cell. Further, bit line capacitance is reduced so that rapid reading can take place without resorting to high current and the concomitant large geometry cells. These and other advantages of the present invention will become apparent to those skilled in the art upon a reading of the following Detailed Description of the Invention together with the drawings.